PCI-SIG Updates on PCIe Specifications

https://www.anandtech.com/show/21531/pcisig-demonstrates-pcie-60-interoperability-at-fms-2024

As the deployment of PCIe 5.0 gains momentum in both datacenter and consumer markets, PCI-SIG is actively preparing for updates to the PCIe specifications. At FMS 2024, discussions among vendors even touched on PCIe 7.0, which promises 128 GT/s capabilities, despite PCIe 6.0 not yet having begun shipping. We engaged with PCI-SIG to gather insights on their current activities and the state of the PCIe ecosystem.

https://www.anandtech.com/show/21531/pcisig-demonstrates-pcie-60-interoperability-at-fms-2024

PCIe 7.0 Specifications

PCI-SIG has made the PCIe 7.0 specifications (version 0.5) available to its members, with full specifications expected to be officially released in 2025. The primary objective is to achieve a data rate of 128 GT/s, facilitating up to 512 GBps of bidirectional traffic through x16 links. Similar to PCIe 6.0, this new specification will utilize PAM4 signaling while ensuring backward compatibility. The drafting process also emphasizes power efficiency and silicon die area considerations.

https://www.anandtech.com/show/21531/pcisig-demonstrates-pcie-60-interoperability-at-fms-2024

Error Correction and Packet Management

The transition to PAM4 signaling introduces higher bit-error rates compared to the previous NRZ scheme. Consequently, a different error correction scheme was necessary for PCIe 6.0. Instead of operating on variable-length packets, PCIe 6.0’s Flow Control Unit (FLIT) encoding now operates on fixed-size packets to enhance forward error correction. PCIe 7.0 will retain these features, ensuring consistency in error management.

Compliance Program and Testing

The integrators list for the PCIe 6.0 compliance program is anticipated to be released in 2025, although initial testing is already underway. This was highlighted during the FMS 2024 demonstration featuring Cadence’s 3nm test chip for its PCIe 6.0 IP offering, alongside Teledyne Lecroy’s PCIe 6.0 analyzer. These timelines align well with the completion dates for specifications and compliance program availability seen in previous PCIe generations.

https://www.anandtech.com/show/21531/pcisig-demonstrates-pcie-60-interoperability-at-fms-2024

Optical Workgroup Developments

We also received updates regarding the optical workgroup. While remaining agnostic to optical technology, the workgroup aims to develop technology-specific form factors, including pluggable optical transceivers, on-board optics, co-packaged optics, and optical I/O. Enhancements to the logical and electrical layers of the PCIe 6.0 specifications are being made to support the new optical PCIe standardization, a process that will also extend to PCIe 7.0 to align with its release next year.

https://www.anandtech.com/show/21531/pcisig-demonstrates-pcie-60-interoperability-at-fms-2024

Cabling Initiatives in PCI-SIG

The PCI-SIG is also pursuing various cabling initiatives. On the consumer front, there has been significant traction for Thunderbolt and external GPU enclosures. However, datacenters and enterprise systems are increasingly adopting cabling solutions as the disaggregation of components, such as storage from the CPU and GPU, proves beneficial for thermal design. Additionally, maintaining signal integrity over longer distances poses challenges for on-board signal traces, making internal cabling solutions advantageous.

OCuLink has emerged as a viable candidate and has been widely adopted as an internal link in server systems. It has also appeared in mini-PCs from some Chinese manufacturers in its external form for the consumer market, although with limited traction. As speeds continue to increase, establishing a widely accepted standard for external PCIe peripherals, or even for connecting components within a system, will become essential.

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